1. Field of the Invention
The invention relates to a method for fabricating MOS transistors, and more particularly, to a method for fabricating a fluorine-containing layer before performing a salicide process.
2. Description of the Prior Art
Field effect transistors are important electronic devices in the fabrication of integrated circuits, and as the size of the semiconductor device becomes smaller and smaller, the fabrication of the transistors also improves and is constantly enhanced for fabricating transistors with smaller sizes and higher quality.
In the conventional method of fabricating transistors, a gate structure is first formed on a substrate, and a lightly doped drain (LDD) is formed on the two corresponding sides of the gate structure. Next, a spacer is formed on the sidewall of the gate structure and an ion implantation process is performed to form a source/drain region within the substrate by utilizing the gate structure and spacer as a mask. In order to incorporate the gate, source, and drain into the circuit, contact plugs are often utilized for interconnection purposes, in which the contact plugs are composed of conducting metals such as tungsten and copper. Nevertheless, the interconnection between the contact plugs and the silicon material of the gate structure and the source/drain region is usually poor, hence a silicide material is often formed over the surface of the gate structure and the source/drain region to improve the ohmic contact between the contact plugs and the gate structure and the source/drain region. Today, the process known as self-aligned silicide (salicide) process has been widely utilized to fabricate silicide materials, in which a source/drain region is first formed, a metal layer comprised of cobalt, titanium, or nickel is disposed on the source/drain region and the gate structure, and a rapid thermal process (RTP) is performed to react the metal layer with the silicon contained within the gate structure and the source/drain region to form a metal silicide for reducing the sheet resistance of the source/drain region.
However, when the silicides are being formed, the atoms within the metal layer will diffuse into the substrate and deplete the silicon within the source/drain region, thereby damaging the original lattice structure of the source/drain region and causing the PN junction between the source/drain region and the silicon substrate to react with the silicon contained within the source/drain region as a result of an overly short distance between the PN junction and the silicide layer. Ultimately, the problems become much worse in the design of ultra shallow junctions (USJ) as the silicides often come in contact directly with the substrate and result in failure of the device.
Referring to FIGS. 1-2, FIGS. 1-2 are illustrate a method for fabricating a MOS transistor according to the prior art. As shown in FIG. 1, a gate structure 66 having a gate dielectric layer 62 and a gate conductive layer 64 is first formed on a substrate 60. A cap layer (not shown) is also deposited on top of the gate 66, in which the cap layer is composed of dielectric material such as silicon nitride. Next, an ion implantation process is performed to form a lightly doped drain 70 in the substrate 60. Next, a liner 67 and a spacer 68 are formed on the sidewall of the gate structure 66 and another ion implantation is performed to form a source/drain region 72 in the substrate 60. Next, a wet cleaning process is performed to remove native oxides and other impurities from the surface of the gate structure 66 and the source/drain region 72, and a degas process is performed to remove the remaining water vapor from the wet cleaning process. Next, a sputtering process is performed to form a metal layer 74 over the surface of the gate conductive layer 64, the spacer 68, and the substrate 60. Subsequently, as shown in FIG. 2, a rapid thermal annealing (RTA) process is performed to react the contact area between the metal layer 74 and the gate conductive layer 64 and the source/drain region 72 into a silicide layer 76. Next, a selective wet etching process is performed to remove the un-reacted metal layer 74 by utilizing mixtures containing ammonia/hydrogen peroxide/water or sulfuric acid/hydrogen peroxide.
In order to prevent the short channel effect of the transistors and improve the interconnect resistance of the integrated circuit, the junction depth of the source and drain needs to be effectively reduced for fabricating transistors containing silicides. However, if the thickness of the silicides on the source and drain is decreased while reducing the junction depth of the source and drain, the interconnect resistance and contact resistance may increase simultaneously. On the other hand, if the depth of the silicides is kept constant, the distance between the PN junction of the source/drain region 72 and the silicon substrate and the silicide layer 76 may become overly short and result in junction leakage. Additionally, the mixture utilized during the wet cleaning process will corrode the liner disposed between the gate electrode and the spacer and cause the silicide to approach the channel area during silicide formation and result in a nickel silicide piping phenomenon.
Moreover, due to high temperature of the PVD chamber or the degas process, the as-deposition formed before the rapid thermal annealing process will result in silicides with polycrystalline structure and degrade the overall thermal stability. In other words, when the treatment temperature is too high or process time of the treatment is too long, the silicides will become pieces of unconnected mass and result in an agglomeration phenomenon and increase the sheet resistance. Additionally, a high temperature will induce a conversion and consume silicon excessively, and cause a spiking phenomenon in the ultra shallow junction or forming a high resistivity structure, such as converting the low resistivity state nickel silicide (NiSi) having less than 20 μΩ-cm to a high resistivity state nickel disilicide (NiSi2) having approximately 50 μΩ-cm.